Schematic Capture is an advanced circuit design tool with support of multi-sheet and multi-level hierarchical schematics. This module of DipTrace delivers a number of features for visual and logical pin connections. Cross-module management ensures that principal circuits can be easily converted to PCB, back annotated, or imported/exported from other EDA, CAD, and netlist formats. Verification and SPICE export for simulation allow for full project analysis.

Visual and Logical Structure
All actions and features are visual and intuitive for the designer. Component pins can be connected visually with wires and buses or logically without wires, using net ports, bus ports, or by name.

Multi-Level Hierarchy
DipTrace hierarchical schematic is based on a multi-sheet circuit structure. Hierarchical blocks can be inserted into the main sheet or into each other as many times as needed. Hierarchy verification reports loop structures if present.

Electrical Rule Check
ERC helps to ensure that engineer works in the error-free design environment. Electrical Rule Check with detailed customization reports short circuits, superimposing and unconnected pins, one-pin nets, and checks connections by pin types.

Import/Export
Schematic capture module allows for exchanging schematics and drawings with other CAD packages (Altium, Eagle, P-CAD, PADS, OrCAD, KiCAD); support of Accel, Allegro, Mentor, OrCAD, PADS, P‑CAD, Protel, Tango netlists.

Advanced Routing Capabilities

PCB Layout is a high-level engineering tool for board design featuring smart manual routing of high-speed and differential signals, shape-based autorouter, advanced verification, and wide import/export capabilities. Design requirements are defined by net classes, class-to-class rules, and detailed settings by object types for each class or layer. DipTrace features design process with real-time DRC, which reports errors on the fly before actually making them. The board can be previewed in 3D and exported for mechanical CAD modeling. Design Rule Check with in-depth detailing, Net Connectivity verification, and comparing to source schematic ensure maximum quality of the final product.

Smart Project Structure

DipTrace is a single environment with direct circuit-to-board converting, updating from schematic, and back annotation. Nets are divided to net classes with custom settings and class-to-class rules. Through and blind/buried vias are organized to Via Styles.

Placement Features

Components can be placed manually by simple drag & drop and special "Placement by list" feature or automatically according to custom settings and with optimized length of traces. For excellent results use a combination of all available placement methods.

Manual Routing

Fixed angle and free traces, arcs and curves, various route modes, segment geometries, layers, real-time DRC and other parameters.

A smart shape-based copper pour system with pour priority and automated settings. Auto fanout for BGA, SOIC, and QUAD footprints.

Teardrops feature for pad/via, trace width change and T-junctions.

High-Speed Autorouter

DipTrace high-class shape-based autorouter with advanced settings is capable of routing complex multi-layer boards, as well as simple single-layer boards with jumper wires. DSN/SES interface provides support for external routers (Specctra, Electra, Topor etc.).

Only for V.i.P